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BI-Phase/Dual Controller
POWER MANAGEMENT Description
The SC2450 can be configured as a dual converter or a bi-phase converter for high current applications. The part is designed for point of use power supplies with 8.5-30V nominal backplane power sources. Multiple supplies can be synchronized together to prevent low frequency harmonics on the backplane. The power dissipation is controlled using a novel low voltage supply technique, allowing high speed and integration, with the high drive currents to ensure low MOSFET switching loss. The use of high speed switching circuits allows very narrow PWM outputs down to 15:1 voltage ratios. Single pin compensation for each channel simplifies development as well as reducing external pin count. Capable of driving MOSFETs via external driver transistors for phase currents beyond 20A.
SC2450
Features
Selectable dual output or bi-phase operation Direct drive for N-channel MOSFETs Undervoltage lockout Synchronization to external clock Multi-converter synchronization Soft start Fast transient response Max duty cycle 45% Output over voltage protection Thermal shutdown 28-Pin SO lead free package available. Fully WEEE and RoHS compliant
Applications
Power supplies for advanced telecoms/datacoms SO IP, Ethernet and PABX power supplies
Typical Application Circuit
Revision: January 17, 2007
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SC2450
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltage Voltage on BST Pins Oscillator Frequency VC C Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 seconds
(1)
Symbol VIN V BST
Maximum 34 42 2 8
Units V V MHz V C/W C/W C C C
JC J A TA TSTG TLEAD
25 80 -40 to +85 -55 to +150 300
Note: (1) Maximum frequency and maximum supply voltage could cause excessive power dissipation in the part.
Electrical Characteristics
Unless specified VIN = 24V, TA = 25C
Parameter Supply Voltage, VIN Supply Current Under Voltage Lockout UVLO Hysteresis Voltage Regulator Pre Regulator Voltage Bgout Voltage Bgout Impedance REGDRV Pin Sink Current Error Amp Input Offset Voltage Input Offset Mismatch Input Impedance Linear Transconductance Internal Oscillator Frequency Frequency Ramp Valley to Peak Ramp Valley to Peak
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Conditions
Min 8.5
Typ
Max 30
Units V mA V mV
ENABLE = 0
30 5.8 400
40
6 CREF = 4.7nF 0.99 1 3 IREGDRV 5
7 1.01
V V K mA
15 4 5 .002
mV mV K A/V
RREF = 30K RREF = 60K VIN = 12V VIN = 24V
2
1 500 1.5 3
MHz kHz V V
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SC2450
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified VIN = 24V, TA = 25C
Parameter External Clock Detect Time Unlock Time Frequency Range High Side Gate Drive Max Duty Cycle Peak Source Peak Sink Low Side Gate Drive Peak Source Peak Sink Sync Drive Timing Min Non-overlap PWM Match Logic Input Pins Input Bias Current Logic Threshold FB2 Disable Threshold Over Current Protection OCP Threshold OC+ I/P Bias Current OC- I/P Bias Current Over Voltage Protection OVP Threshold Thermal Shutdown
Note:
Conditions
Min
Typ
Max
Units
Rise Time < 50ns 10 0.27
2 50 1
s s MHz
45 CLOAD = 10nF CLOAD = 10nF 1 1
% A A
CLOAD = 10nF CLOAD = 10nF
2 2
A A
CLOAD = 1nF Fet Drive < 1V 50% Duty Cycle, FOSC = 1MHz
20 -1
50 1
ns %
VIN = 0 - 5V
-10 0.8 VCC - 0.7V
10
A V V
103 VIN = 24V
115 700 50
127
mV A A
120 150
% C
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC2450
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Part Number SC2450ISWTR SC2450ISWTRT(2) S C 2450E V B PACKAGE(1) SO-28 TAMB (TA) -40 - +85C
SC2450 Evaluation Board
Notes: (1) Only available in tape and reel packaging. A reel contains 1000 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
(28-Pin SOIC)
Block Diagram
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SC2450
POWER MANAGEMENT Pin Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name FB1 COMP1 NC BG FB2 COMP2 REGDRV ENABLE PHASE2 DRVH2 BSTH2 DRVL2 BSTL2 VCC BSTL1 DRVL1 BSTH1 DRVH1 PHASE1 PGND OC+ OC-2 OC-1 EXTCLK CLKOUT NC AGND RREF Pin Function Feedback for channel 1. Compensation for channel 1. No connection. 1V reference for error amplifiers, 3K source impedance. Feedback for channel 2. Compensation for channel 2. Regulator drive for external pass transistor. Enable threshold is 2.05 V, connect to ground to disable. Phase node input for channel 2. Gate drive for high side channel 2. Bootstrap input for high side channel 2. Gate drive for low side channel 2. Supply for low side channel 2. Pre-regulated IC power supply. Supply for low side channel 1. Gate drive for low side channel 1. Bootstrap input for high side channel 1. Gate drive for high side channel 1. Phase node input for high side channel 1. Power ground. Overcurrent comparator inverting input. Overcurrent comparator non-inverting input for channel 2. Overcurrent comparator non-inverting input for channel 1. External clock, converter locks to this input when a valid signal is present. Clock out, logic level drive to provide synchronizing signal for other converters. No connection. Analog ground. External reference resistor for internal oscillator and ramp generator.
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SC2450
POWER MANAGEMENT Typical Application
Schematic for Two Channel Operation
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SC2450
POWER MANAGEMENT Typical Application (Cont.)
Bill of Material for Two Channel Operation
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Qty Reference 8 3 2 1 2 1 6 2 2 3 1 11 4 4 2 2 C1 - C8 C9,C24,C25 C10,C11 C12 C13,C14 C15 C16,C19,C20,C21,C22,C23 C17,C18 C26,C27 C28,C29,C50 C30 C31,C32,C33,C36,C37,C40,C41,C42,C43,C44,C45 C34,C35,C38,C39 D1,D2,D5,D6 D3,D4 L1,L2 Part Number/Value 0.47F, 50V, Cer. 0.33F, Cer., 1206 22nF, Cer., 1206 0.1F, Cer., 1206 10nF, Cer., 1206 47pF, Cer., 1206 22F, 35V, Tant. 680F, 35V, Alum. 2.2nF, Cer., 1206 1.0nF, Cer., 1206 1.0F, Cer., 1206 10F, Cer., 1206 1500F, 6.3V, Alum. 1A, 40V, Schottky, MELF, 1N5819M 3A, 40V, Schottky, 30BQ040 Inductor, 9 turns Manufacturer Any Any Any Any Any Any Any Any Any Any Any Any Any Any Any Magnetics: Kool Mu P/N: 77206-A7 Fairchild P/N: FDB7030BL BCP56CT Any Any Any Any Any Any
17 18 19 20 21 22 23 24
4 1 2 2 4 1 2 1
M1,M2,M3,M4 Q1 R1,R3 R4,R6 R2,R5,R7,R11 R8 R9,R10 R12
N-Channel MOSFET, TO263AB 80V, 1A, NPN, Med. Pwr. SOT-223 2.2, 5%, 1206 4.7, 5%, 1206 1.0, 5%, 1206 56k, 5%, 1206 2.2k, 5%, 1206 Chip resistor, 0.005, 1W, 1%, 2512
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SC2450
POWER MANAGEMENT Typical Application (Cont.)
Bill of Material for Two Channel Operation (Cont.)
Item 25 26 27 28 29 30 31 32 33 34 35 36 37 Qty Reference 4 1 2 1 1 2 1 1 1 1 1 0 1 R13,R14,R15,R16 R17*,R19,R31* R20,R21 R22 R23 R26,R27 R28 R29 R34 R36 R37 Roc1*,Roc2* SC2450 Part Number/Value 2.2, 1/4W, 5%, 1210 Chip resistor, 0, 1206 1.00k, 1%, 1206 2.32k, 1%, 1206 4.02k, 1%, 1206 20, 5%, 1206 10, 5%, 1206 51, 5%, 1206 15k, 5%, 1206 68.1k, 1%, 1206 10.0k, 1%, 1206 TBD, 1%, 1206 Bi-Phase/Dual Controller, SO-28W Manufacturer Any Any Any Any Any Any Any Any Any Any Any Any Semtech Corp. P/N: SC2450ISW 805-498-2111
Notes: 1. * Indicates optional parts. 2. Some parts are selected due to availability or lead time, and are not optimized.
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SC2450
POWER MANAGEMENT Typical Application (Cont.)
Schematic for Bi-Phase Operation
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SC2450
POWER MANAGEMENT Electrical Characteristic Curves
Two Channel Operation Efficiency in Two-Channel Application Circuit (5V/12A, 3.3V/18A)
Overall System Efficiency vs. Overall Load (W ) of the 5V and 3.3V channels
95.00% 90.00% 85.00% 80.00%
Efficiency
Efficiency
75.00% 70.00% 65.00% 60.00% 0 20 40 60 Output Power (W ) 80 100 120
Phase Node Waveform of Two-Channel Application Circuit (Vin = 24V, Load Current = 12A for 5V, Load Current = 18A for 3.3V)
ch1: Vphase5V; ch2: Vphase3.3V
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SC2450
POWER MANAGEMENT Electrical Characteristic Curves (Cont.)
3.3V Channel Gate Waveform (Vin = 24V, Load Current = 18A)
ch1: VgateH; ch2: VgateL
5.0V Channel Gate Waveform (Vin = 24V, Load Current = 12A)
ch1: VgateH; ch2: VgateL
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SC2450
POWER MANAGEMENT Electrical Characteristic Curves (Cont.)
Start-up (Vin = 24V, Vout1 = 5.0V/12A, Vout2 = 3.3V /18A)
ch1: Vout5.0V; ch2: Vout3.3V
Bi-Phase Operation (Vout = 3.3V, Max. Load Current = 20A) Efficiency in Bi-Phase Application Circuit (3.3V/20A)
Overall System Efficiency vs. iLoad
90.00%
85.00%
80.00% Efficiency
75.00%
Overall Efficiency
70.00%
65.00%
60.00% 0 5 10 Load Current (A) 15 20
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SC2450
POWER MANAGEMENT Electrical Characteristic Curves (Cont.)
Phase Node Waveform (Vin = 24V, Vout = 3.3V, Load Current = 20A)
ch1: Vphase1; ch2: Vphase2
Gate Waveform (Vin = 24V, Vout = 3.3V, Load Current = 10A/phase)
ch1: VgateL; ch2: VgateH
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SC2450
POWER MANAGEMENT Electrical Characteristic Curves (Cont.)
Start-up (Vin = 24V, Vout = 3.3V, Load Current = 5A/phase)
ch1: Vout
Theory of Operation
The SC2450 employs a voltage mode control with feed forward to provide fast output response to load and line transients. The SC2450 has two outputs, which can be used to generate two separate supply voltages or can be combined in bi-phase operation to generate one single supply voltage. The internal reference is trimmed to 1 V with +/-1% accuracy, and the outputs voltages can be adjusted by two external resistors. In bi-phase operation, the dual switching regulators are operated 180 out of phase. Load current sharing between phases is normally required, and this can be achieved by using precise feedback voltage divider resistors (typically 0.1%) to match individual phase output voltage. In addition, small drooping resistors ( could be PCB traces) are employed at the output of each phase to enhance phase current balance. PWM Control Changes on the output voltages are fed to the inverting input of the Error Amplifiers, by the FB1 and FB2 pins, and compared with the internal 1 V reference. The compensation to the transconductance amplifier is achieved by connecting a capacitor in series with a resistor from the COMP1 and COMP2 pins to AGND respectively. The error signal from the error amplifier is compared to the saw tooth waveform by the PWM comparator, and
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matched timing signal is generated to control the upper and lower gate drives of the two phases. A single Ramp signal is used to generate the control signals for both of phases, hence the maximum duty cycle is less than 50%. Oscillator Frequency Selection The sawtooth signal is generated by charging an internal capacitor with a current source. The charge current is set by an external resistor connected from the RREF pin to AGND. The oscillator frequency and the external resistance follow an inversely proportional relationship. Feed Forward The SC2450 incorporates a voltage feed forward scheme to improve line transient immunity when changes of the input voltage occur. As the input voltage changes, the ramp valley to peak voltage of the internal oscillator follows this change instantly. As a result the output voltage will have minimum disturbance due to the input line change. Synchronized Operation The internal oscillator can be synchronized to an external clock operating in the range of 270 kHz to 1 MHz. The switching frequency of each channel is one half of the oscillator frequency. The oscillator clock is also available externally through the CLKOUT pin and can be used to provide synchronization for other converters.
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SC2450
POWER MANAGEMENT Theory of Operation (Cont.)
Bias Generation A 6-7 Volt supply voltage is required to power up the SC2450. This voltage could be provided by an external power supply or derived from VIN through an external pass transistor. REGDRV is the control signal to the base of the pass transistor that will regulate VCC. The voltage at the VCC pin is compared to the internal voltage reference, and the REGDRV pin can sink up to 5 mA current to regulate the voltage at the VCC pin. Enable If the ENABLE pin is connected to logic high, the SC2450 is enabled, while connecting it to ground will put the device into disabled mode. The ENABLE pin can also be configured as input UVLO through input voltage divider resistors. The controller will be enabled when the ENABLE pin voltage reaches 2.05 V, and will be disabled with 400 mV hysteresis. Under Voltage Lockout Under Voltage lockout (UVLO) circuitry senses VCC through a voltage divider. If this signal falls below 5.8 V, with a typical hysteresis of 400 mV, the BG pin is pulled low by an internal transistor causing the lower MOSFET gate to be on and the upper MOSFET gate off for both phases. Over Voltage Protection The SC2450 provides OVP protection for each output individually. Once the converter output voltage exceeds 120% nominal output voltage, the lower MOSFET gates are latched on and the upper MOSFET gates are latched off. The latch is then reset once the OVP condition is removed. Soft Start An external capacitor at the BG pin is used to set up the Soft Start duration. The capacitor value, in conjunction with the internal 3K resistor at the BG pin, control the duration to bring up the bandgap to its final level. As the BG capacitor is being charged through the internal resistor, the PWM pulse opens accordingly until the bandgap is charged completely. This controlled start up of the PWM prevents output voltage overshoot, unnecessary component stress, and noise generation during start up.
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Over Current Protection The SC2450 current limit provides protection during an over current condition. A sense resistor or PCB trace can be used to sense the input supply current. The over current protection trip point is determined by the voltage drop across the sense resistor. Once this voltage drop exceeds 115 mV, OCP protection circuit will be triggered. Due to component and layout parasitics, filtering might be necessary across the OC+ and OC- pins. It is recommended to use 20 Ohm resistor and 10 nF capacitor for filtering. The OCP accuracy may be affected by non-ideal PCB layout and MOSFET variations. To accommodate these variations, the OCP threshold can be externally adjusted by a voltage divider across the sense resistor to attenuate the voltage drop across the sense resistor, so that increase the OCP threshold accordingly. See application circuits. Once an over current condition occurs, the lower MOSFET gates are latched on and the upper MOSFET gates are latched off. The latch is then reset at the beginning of the next clock cycle. The cycle is repeated indefinitely until the over current condition removed. Thermal Shutdown In addition to current limit, the SC2450 monitors over temperature condition. The over temperature detection will shut down the part if the SC2450 die temperature exceeds 150C, and will auto reset once the die temperature is dropped down. Gate Drive The SC2450 integrates high current gate drivers for fast switching of large MOSFETs. The high-side gates can be switched with peak currents of 1 Amp, while the larger low-side gates can be switched with peak currents of 2 Amps. A cross conduction prevention circuitry ensures a non-overlapping operation between the Upper and Lower MOSFETs. This prevents false current limit tripping and provides high efficiency.
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SC2450
POWER MANAGEMENT Control Loop Design
R2 R1 0 Error-Amp + R + Vbg 0 0 C 0 + Vin Co Ro Rc Verror Gpwm Duty L
The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The following design procedures are recommended to accomplish the goal: (1) Calculate the corner frequency of the output filter:
FO := 1 2 * * L * CO
0
Fig. 1. SC2450 control model.
(2) Calculate the ESR zero frequency of the output filter capacitor:
Fesr := 1 2 * * R C * CO FSW 5
The control model of SC2450 can be depicted in Fig. 1. This model can also be used in Spice kind of simulator to generate loop gain Bode plots. The bandgap reference is 1 V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. The error amplifier is transconductance type with fixed gain of:
GERROR : = 0.002 A V
(3) Check that the ESR zero frequency is not too high.
Fers <
The compensation network includes a resistor and a capacitor in series, which terminates from the output of the error amplifier to the ground. This device uses voltage mode control with input voltage feed forward. The peak-to-peak ramp voltage is proportional to the input voltage, which results in an excellent performance to reject input voltage variation. The PWM gain is inversion of the ramp amplitude, and this gain is given by:
GPWM : = 1 VRAMP
If this condition is not met, the compensation structure may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank to correct the output filter corner frequency and the ESR zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. It is not recommended to use only high frequency multi-layer ceramic capacitors for output filter.
(4) Choose the loop gain cross over frequency (0 dB frequency). It is recommended that the crossover frequency is always less than one fifth of the switching frequency or the output ripple frequency in bi-phase mode operation:
FX _ OVER FSW 5
where the ramp amplitude (peak-to-peak) is 3 volts when input voltage is 24 volts. The total control loop-gain can then be derived as follows:
1 s. R. C . T( s) T o. s. R. C 1 s. R c. C o 1 s. R c. C o L Ro s L. C o. 1
2.
If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The resistor in the compensation network can then be calculated as:
R 1 G pwm. V in. G error . F esr Fo
2
.
F x_over F esr
.
Vo V bg
Rc Ro
when:
F o < F esr< F x_ o ver
where
.. .. T o G error.V in.G pwm .R .
R2 R1 R2 16
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SC2450
POWER MANAGEMENT Control Loop Design (Cont.)
or
R 1 . Fo
2
Step 1. Output filter corner frequency
. F x_over Fo . Vo V bg
Fo = 1.453 KHz Step 2. ESR zero frequency: Fesr = 2.653 KHz Step 3. Check the following condition:
G pwm. V in. G error F esr
when
F esr< F o < F x_over
(5) The compensation capacitor is determined by choosing the compensator zero to be about one fifth of the output filter corner frequency:
F zero C Fo 5
< F ers
F sw 5
Which is satisfied in this case. Step 4. Choose crossover frequency and calculate compensator R:
zero
1 2 . . R . F
(6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equations provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this design procedure ensures a healthy phase margin. An example is given below to demonstrate the procedure introduced above. The parameters of the power supply are given as:
V V I F
Fx_over = 30 KHz R = 5.89 K Step 5. Calculate the compensator C: C = 92.98 nF Step 6. Generate Bode plot and check the phase margin. In this case, the phase margin is about 85C that ensures the loop stability. Fig. 2 shows the Bode plot of the loop.
in o o
:= 24 V
:= 2.5 V := 20 A
:= 150 KHz sw L := 4 H
C
o c 1 2
:= 3000 F := 0.02 := 1.5 K := 1.0 K
R R R
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SC2450
POWER MANAGEMENT Control Loop Design (Cont.)
L o o p G ain M ag (dB )
10 0
50 m ag ( i) 0
50 10 10 0 3 1 10 F 4 1 10 i 5 1 10 6 1 10
L o o p G ain P h ase (D egree)
0 45 p h ase( i) 90 13 5 18 0 10 10 0 3 1 10 F 4 1 10 i 5 1 10 6 1 10
Fig. 2. Bode plot of the loop
Layout Guidelines
Good layout is necessary for successful implementation of the SC2450 bi-phase/dual controller. Important layout guidelines are listed below. 1). The high power parts should be laid out first. The parasitic inductance of the pulsating power current loop (start from positive end of the input capacitor, to top MOSFET, then to bottom MOSFET back to power ground) must be minimized. The high frequency input capacitors and top MOSFETs should be close to each other. The freewheeling Schottky diode, the bottom MOSFET snubber, and the bottom MOSFET should be placed close to each other. The MOSFET gate drive and current sense loop areas should be minimized. The gate drive trace should be short and wide. 2). The layout of the two phases should be made as symmetrical as possible. The SC2450 controller should be placed in the center of the two phases. Please see evaluation board layout as an example. 3). Separate ground planes for analog and power should be provided. Power current should avoid running over the analog ground plane. The AGND is star connected to the PGND at the converter output to provide best possible ground sense. Refer to the application schematics, certain components should be connected directly to the AGND. 4). If a multi-layer PCB is used, power layer and ground layer are recommended to be adjacent to each other. Typically the power layer is on the top, followed by the ground layer. This results in the least parasitic inductance in the MOSFET-capacitor power loop, and reduces the ringing on the phase node. The rest of the layers could be used to run DC supply traces and signal traces. An example of a two-layer PCB layout is given below to illustrate these layout principles.
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SC2450
POWER MANAGEMENT Layout Guidelines (Cont.)
Component Side (TOP)
Copper (TOP)
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SC2450
POWER MANAGEMENT Layout Guidelines (Cont.)
PG N D
A GN D
Copper (BOTTOM)
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SC2450
POWER MANAGEMENT Outline Drawing - SO-28
A
N
e
D
DIM
A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.093 2.65 .104 2.35 .004 0.30 .012 0.10 .081 2.55 .100 2.05 .020 0.31 0.51 .012 .008 0.33 .013 0.20 .701 .705 .709 17.80 17.90 18.00 .291 .295 .299 7.40 7.50 7.60 10.30 BSC .406 BSC 1.27 BSC .050 BSC .010 .030 0.25 0.75 .016 1.04 .041 0.40 (1.04) (.041) 28 28 0 8 0 8 0.10 .004 0.25 .010 0.33 .013
2X E/2
E1
E
ccc C
2X N/2 TIPS
1
2
3
e/2 B D
aaa C SEATING PLANE C
A2 A bxN bbb A1 C A-B D GAGE PLANE SIDE VIEW SEE DETAIL
h h H c
A
0.25
NOTES: 1. 2. DATUMS -A- AND -B-
L (L1) DETAIL
01
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). TO BE DETERMINED AT DATUM PLANE -H-
A
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-013, VARIATION AE.
Land Pattern - SO-28
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.362) .276 .050 .024 .087 .449 (9.20) 7.00 1.27 0.60 2.20 11.40
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. REFERENCE IPC-SM-782A, RLP NO. 307A.
2.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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